Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - ip core

Search list

[Crack Hack] aes_core

Description: aes_core verified verilog ip core-aes_core verified verilog ip core
Platform: | Size: 11264 | Author: 邓婕 | Hits:

[VHDL-FPGA-Verilog] fftip

Description: Quartus中fft ip core的使用-Quartus in the use of fft ip core
Platform: | Size: 449536 | Author: mikecool | Hits:

[VHDL-FPGA-Verilog] altera_up_avalon_sd_card_interface

Description: 基于VHDL的SD卡IP核，Altera公司推出的大学计划！最新版本9.0-VHDL-based IP core of the SD card, Altera' s university program launched! The latest version 9.0
Platform: | Size: 264192 | Author: 兔子 | Hits:

[VHDL-FPGA-Verilog] lcd_drv

Description: IP core for LCD controller of Xilinx FPGA
Platform: | Size: 2048 | Author: phong duong | Hits:

[VHDL-FPGA-Verilog] power_gating

Description: ieee paper on power gating and can be use full for implementing on ip core
Platform: | Size: 980992 | Author: devil412 | Hits:

[VHDL-FPGA-Verilog] ethernet

Description: 以太网MAC层IP核设计Veriolg代码，包括TESTBECH平台和设计文档-Ethernet MAC layer IP core design Veriolg code, including TESTBECH platform and design documents
Platform: | Size: 844800 | Author: wm | Hits:

[VHDL-FPGA-Verilog] sdram_ver_134

Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is based Xilinx FPGA Playform.
Platform: | Size: 108544 | Author: peace | Hits:

[VHDL-FPGA-Verilog] sdram_vhd_134

Description: This code is a SDRAM Controller IP Core for FPGA to interface with SDRAM Memory. This code is Verilog. This code is based Xilinx FPGA Playform.
Platform: | Size: 488448 | Author: peace | Hits:

[VHDL-FPGA-Verilog] UARTipcore

Description: 这是一个关于UART的IP核，用VHDL写的。经过本人的鉴证，非常实用并且写的非常好。-This is one of the IP core on the UART, using VHDL written. After my verification, very practical and very well written.
Platform: | Size: 22528 | Author: 11 | Hits:

[Other] PIC10_RISC_Verilog

Description: The PIC10-compatible microcontroller core was implemented as part of a client project where a small PIC-compatible microprocessor IP Core was needed to be integrated into a CPLD or FPGA. This allowed extremely fast but yet simple firmware programming of an embedded system that did not contain a dedicated microcontroller. The CPU PIC10 CPU IP Core was modeled after the Microchip PIC10F200/ 202/204/206 series single-chip microcontroller.
Platform: | Size: 47104 | Author: hfayed | Hits:

[Other] altera_nand_controller

Description: Altera合作伙伴Eureka Technology.和Cast Inc.为Altera FPGA芯片定制的Nand flash controller IP core-Altera partner Eureka Technology. And the Cast Inc. For the Altera FPGA chip custom Nand flash controller IP core
Platform: | Size: 296960 | Author: Trevor | Hits:

[VHDL-FPGA-Verilog] 8086IP

Description: 用硬件描述语言编写的8086 IP CORE-Using hardware description language of the 8086 IP CORE
Platform: | Size: 71680 | Author: andy | Hits:

[VHDL-FPGA-Verilog] IPcore

Description: 非常有用的IP核资源，里面包含了JTAG,MEMORY,PCI，SDRAM和USB1.1等内容，期望对大家有用-A very useful IP core resources, which includes the JTAG, MEMORY, PCI, SDRAM, and USB1.1 and other content, expectations for all of us
Platform: | Size: 903168 | Author: 李同滨 | Hits:

[VHDL-FPGA-Verilog] C8051_mega_core.tar

Description: 8051单片机软核，测试代码和仿真环境，可直接上fpga使用，是一个成熟的ip核。经本人仿真以及在fpga上测试，完全正常。-8051 soft ip core, testbench, simulation environment
Platform: | Size: 719872 | Author: sdwsh | Hits:

[VHDL-FPGA-Verilog] altera_up_avalon_sd_card_interface_91

Description: 修改后的Altera大学计划IP Core，可用于QII9.1及9.1SP1-Revised Altera University Program IP Core, can be used for QII9.1 and 9.1SP1
Platform: | Size: 319488 | Author: Royal Wang | Hits:

[VHDL-FPGA-Verilog] fifoed_avalon_uart9.1_applicaton

Description: 用于Altera Avalon总线的、具有FIFO缓冲的Uart数据串口IP核以及应用于Nios2的、真正可运行的、容易移植的C代码。-Fifoed avalon uart IP core and C code for the IP core.
Platform: | Size: 205824 | Author: xmar | Hits:

[ARM-PowerPC-ColdFire-MIPS] arm7verilog

Description: ARM 7 免费ip 核， verilog语言描述-arm7 free ip core, verilig DHL
Platform: | Size: 1400832 | Author: zdh | Hits:

[VHDL-FPGA-Verilog] CANProtocolControllerIPCoreinVerilog

Description: 一种基于CAN协议的IP核源代码，用Verilog语言实现-CAN Protocol Controller IP Core in Verilog.
Platform: | Size: 67584 | Author: Nicholas | Hits:

[Software Engineering] USB2.0DeviceControllerIPCoreDesignandVerification.

Description: USB2．0设备控制器IP核的设计与验证-USB2.0 Device Controller IP Core Design and Verification
Platform: | Size: 432128 | Author: 许云涛 | Hits:

[Software Engineering] FPGA_RS232

Description: 为增加系统稳定性，减小电路板面积，提出一种基于FPGA的异步串行口IP核设计。该设计使用VHDL硬件描述语言时接收和发送模块在Xilinx ISE环境下设计与仿真。最后在FPGA上嵌入UART IP核实现电路的异步串行通信功能。该IP核具有模块化、兼容性和可配置性，可根据需要实现功能的升级、扩充和裁减。-In order to increase system stability, reduce board space, presents a FPGA-based asynchronous serial port IP-core design. The design using the VHDL hardware description language to receive and transmit modules in Xilinx ISE design and simulation environment. Finally, embedded UART IP core on the FPGA circuit implementation of the asynchronous serial communications. The IP core has a modular, compatibility and configurability, can achieve the functionality needed upgrade, expansion and reduction.
Platform: | Size: 215040 | Author: jalon | Hits:
« 1 2 3 4 5 6 78 9 10 11 12 ... 50 »

CodeBus www.codebus.net